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3rd IFAC Workshop on Discrete-Event System Design (2006)
Discrete-Event System Design, Volume# 3 | Part# 1
Location: University of Zielona Gora, Poland
National Organizing Committee Chair: Adamski, Marian
International Program Committee Chair: Gomes, Luis; Wegrzyn, Marek
Conference Editor: Adamski, Marian; Gomes, Luis; Wegrzyn, Marek; Labiak, Grzegorz
ISBN: 978-3-902661-63-0
Start Date: 2006-09-13
End Date: 2006-09-15
| Paper Title | Authors | Updated | |
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| Time analysis of protocol converters for wireless transmission in Modbus networks | Zielinski, Bartlomiej | 2006-09-13 |
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Authors: Zielinski, Bartlomiej
Abstract: The paper presents an example of protocol converter that makes it possible to introduce low-power, low-speed wireless transmission into an existing Modbus network without any major modifications. Hardware and software parts of the converters as well as protocol conversion rules are shortly described. Basic time analysis of protocol converter influence upon transmission time in Modbus network is presented.
Keywords: communication networks,communication protocols
Identifier: 10.3182/20060926-3-PL-4904.00046
Conference: 3rd IFAC Workshop on Discrete-Event System Design (2006)
Location: University of Zielona Gora, Poland
Start Date: Wed Sep 13 2006 - End Date: Fri Sep 15 2006
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| UML in design of ASIP | Masarík, Karel; Hruska, Tomás | 2006-09-13 |
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Authors: Masarík, Karel; Hruska, Tomás
Abstract: There are many possibilities how to describe the architecture of the embedded system eventually of the whole microprocessor. The description is realized usually using any special language, which only rarely provides a formal description of the architecture. The formal description is useful for an easily verification of the most critical parts of the architecture. Our task deals with the formal description of the Application Specific Instruction set Processors (ASIP) in UML. Due to the lower complexity of this type of processor, it is possible to generate automatically the software toolset from the model, which provide fluent development of the microprocessor's applications. The task is to provide the methodology for fully automatized design of microprocessor base on the UML description.
Keywords: ASIP,architecture description language,UML
Identifier: 10.3182/20060926-3-PL-4904.00035
Conference: 3rd IFAC Workshop on Discrete-Event System Design (2006)
Location: University of Zielona Gora, Poland
Start Date: Wed Sep 13 2006 - End Date: Fri Sep 15 2006
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| UML manufacturing system model analysis using Petri nets | Tomasz, Kowalski | 2006-09-13 |
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Authors: Tomasz, Kowalski
Abstract: The net verification method of Discrete Event-Driven Systems modelled by UML activity diagrams is proposed. Verification is made in a formal way by suitable procedure called Activity Diagram to Net verifier (is short: ADN-verifier). First, conversion of activity diagrams (AD) into Coloured Petri net (CPN) is proposed. Next, dynamic properties of CPN are analysed, such as: rules independence, completeness, simulation of AD by CPN, detection of any structural incorrectness in AD model. The method was extended to identify incorrectness in the AD model. Application of ADN-verification method is presented by example from manufacturing systems domain.
Keywords: discrete event system,modelling,UML,Petri nets,verification,fault identification
Identifier: 10.3182/20060926-3-PL-4904.00036
Conference: 3rd IFAC Workshop on Discrete-Event System Design (2006)
Location: University of Zielona Gora, Poland
Start Date: Wed Sep 13 2006 - End Date: Fri Sep 15 2006
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